Magnetic core branching shift register arrangement



Oct. 7, 1969 J. E. scHwENKl-:R 3,471,837

MAGNETIC CORE BRANCHING SHIFT REGISTER ARRANGEMENT 4 Sheets-Sheei FiledDec. 17, 1964 IIQHIIII 4 Sheets-Sheet i J. E. SCHWENKER MAGNETIC COREBRANCHING SHIFT REGISTER ARRANGEMENT Cet. 7, 1969 Filed Dec. 17, 1964 YQN m. m./ i S (s s Q s NW mi E m0 N* `W Go www \mw\ mm uw um mw mw new?@M new www *www @uw 6N 5w l R Nm Dawg Qzmw m v v m 5 w m v www m N t G`N N Gw v w m m HE QQ R f I r l l. l m mm mm mm BEB bfc@ m m` @Pi Oct. 7,1969 J. E. scHwENKER 3,471,837

HAGNETIC CORE BRANCHING SHIFT REGISTER ARRANGEMENT Filed Dec. 17, 1964 4Sheets-Sheet F/G. 2A

CORE CORE ro CURE/3 m l @Loc/f 25/2 0 SGI/RC CLOCK 73 L-SOURCE F G. 2C

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Oct. 7, 1969 J. E. SCHWENKER MAGNETIC CORE BRANCHING SHIFT REGISTERARRANGEMENT Filed Dec. 17, 1964 4 Sheets-Sheet i TRANSM/T 7'0 BRA/VCH.3/

3,471,837 MAGNEIIC CORE BRANCHING SHIFT REGISTER ARRANGEMENT lohn E.Schwenker, Millington, NJ., assignor to Bell Telephone Laboratories,Incorporated, New ork, NY.,

a corporation of New York Filed Dec. 17, 1964, Ser. No. 418,994 Int. Cl.Gllb /00 US. Cl. 340-174 19 Claims ABSTRACT 0F THE DISCLOSURE Abranching balanced magnetic shift register is developed for propagatinginformation signals through selected branches of the register. A linkedset of 211 balanced magnetic cores is included in branch point registerstage for selectively routing information signals among 2x1-1 branchesvia 211-1 mutually orthogonal signal windings so that clockenergizations supplied to half of the cores induce a net transfer ofinformation signals in only a predetermined one of the signal windings.The particular branch winding selected depends upon the sequence inwhich clock signals are applied to the balanced magnetic cores.

This invention relates to magnetic core circuits and, more specifically,to a ferromagnetic core arrangement which functions as a branching shiftregister.

Electronic and magnetic circuit combinations which register a pluralityof information digits at discrete storage locations and advance thestored information at periodic time intervals are well known. Thesecircuits typically include a plurality of shifting stages which receivebinary input signals and supply corresponding digits to their outputterminals delayed in time from the input quantities. One extensivelyemployed shift register embodiment includes a plurality of set-resetip-op circuits in one-to-one correspondence with the maximum number ofinformation digits to be stored in the register at any single time. Aclock source is connected to either the set or reset terminal of eachflip-flop, and the output of each register stage is connected by adelaying element to the remaining input terminal of the next succeedingstage, with an input information source being connected to the secondinput terminal of the lirst stage flip-flop. Information is thenregistered and propagated down the chain of shift register stages byalternate energizations supplied by the information source and the clocksource.

In the above and other prior art registers, information ischaracteristically translated through a single set of cascaded shiftingstages, either in a unidirectional or bidirectional mode of operation.However, a plurality of circuit applications, eg., digital multiplexingsystems, require the selective transfer of information among a pluralityof signal channels, or branches.

It is therefore an object of the present invention to provide abranching magnetic core shift register.

More specifically, an object of the present invention is the provisionof a shift register embodiment which selectively translates digitalinformation through a plurality of signal shifting register branches.

Another object of the present invention is the provision of a highlyreliable magnetic core branching shift register which may advantageouslybe inexpensively and easily fabricated.

These and other objects of the present invention are realized in aspecific, illustrative, branching shift register wherein digitalinformation bilaterally propagates through selected register branches.The arrangement includes a plurality of balanced multiapertured magneticnited States Patent O 3,471,837 Patented Oct. 7, 1969 ice core stages,with a digital bit translating through an associated shifting stageresponsive to four impressed clock phase signals.

A linked set of 2n cores is included in the shifting stage associatedwith each register branching point to selectively route informationamong a total of 211-1 incoming and outgoing branches via 2-1 mutuallyorthogonal coupling windings. The particular information propagatingpath is dependent upon the specific manner in which the clock signalsare supplied to the cores.

It is thus a feature of the present invention that a magnetic core shiftregister include a plurality of information shifting branches and a setof cores at each register branch point for selectively routing digitalinformation therebetween.

It is another feature of the present invention that a branching shiftregister include 2n-l digital information translating channels, 2nsquare loop magnetic storage elements, 211-1 signal windings coupled ina mutually orthogonal relationhsip to the cores and selectivelyconnected to the information channels, and information routing clockcircuitry for selectively switching a rst set of .2n-1 of the cores and,thereafter, switching the remaining 29-1 of the cores.

A complete understanding of the present invention and of the above andother features, advantages and variations thereof may be gained from aconsideration of the following detailed description of an illustrativeembodiment thereof presented hereinbelow in conjunction with theaccompanying drawing, in which:

FIGS. 1A and 1B respectively comprise the left and right portions of adiagram depicting a specific, illustrative magnetic core branching shiftregister which embodies the principles of the present invention;

FIG. 2A is a diagram depicting in detail a selected magnetic core 12included in FIG. 1A;

FIGS. 2B through 2D respectively illustrate three distinct magneticstates which obtain in the core 12 shown in FIG. 2A;

FIG. 3 illustrates a plurality of magnetic states characterizing a rstselected set of cores included in FIG. 1A; and

FIG. 4 illustrates a plurality of magnetic states characterizing asecond selected set of cores included in FIG. 1B.

Referring now to FIGS. 1A and 1B, hereinafter referred to as compositeFIG. 1, there is shown a specific, illustrative, magnetic core shiftregister wherein digital information selectively propagates throughthree shifting branches 30 through 32. Each of the branches 30 through32 includes a plurality of shifting stages 10, with the registerbranches being respectively connected at their extremities to anassociated plurality of digital information terminals 40 through 42, andto a common magnetic core branching stage 5S. The digital terminals 40through 42 are adapted to selectively supply and receive digitalinformation, wherein binary 1 and O signals, shown in FIG. l alongsidethe terminal 40, are respectively manifested by bipolar currents whichfirst flow towards or away from the receiving structure.

Four clock sources 71 through 74 are employed to respectively supply aphase l through a phase 4 clock Voltage pulse to the shifting and branchpoint register stages 1t) and 55. The clock signals are cyclicallygenerated in the sequential order phase 1 through phase 4 (Q1 through@4). Finally a clock signal distribution circuit 70, of a type andnature more fully described hereinafter, is utilized to selectivelyconnect the phase 3 and phase 4 clock sources 73 and 74 to a pluralityof transmitting windings 2665 through 2668. These windings 26 arecoupled in accordance with the subscripts associated there- 3 with to aset of cores 65 through 68 in a manner described hereinbelow.

A representative shifting stage 10, included in the shifting branch 30,is illustrated in detail in FIG. 1 and comprises four informationreceiving cores 11 through 14 and four data transmitting cores 15through 18. It is noted at this point, that functional designations suchas receiving, transmitting and the like correspond to an informationtranslation from left to right in FIG. l. This digital propagationdirection is presumed to obtain unless a contrary direction isparticularly stated.

The stage 10 of the branch 30 further comprises incoming and outgoingcoupling windings and 22 which are respectively inductively linked inthe relative polarity relationships shown in FIG. 1 to the cores 11through 14 and 15 through 18, and also an intra-stage short-circuitedcoupling loop 21 which is coupled to each of the cores 11 through 18. Inaddition, a different receiving winding 25 and transmitting winding 26,of a nature disclosed hereinafter, are coupled to each of the cores 11through 18 and connected to the particular clock source 71 through 74indicated by the phase (fr) designation shown alongside the winding inFIG. l. More specically, the receiving winding 25 coupled to a core isconnected to the clock phase given by the receiving (Rec.) numeral shownassociated therewith in FIG. l, and the transmitting winding 26 coupledthereto is connected to the clock phase given by the transmitting (Tr.)numeral also illustrated therein.

The core 12, which is typical of each of the ferromagnetic coresincluded in the FIG. l branching shift register, is shown in detail inFIG. 2A and comprises a balanced multiapertured structure of a typedescribed in detail in a pending application by J. N. Brown, Jr., and E.E. Nyewhall, Ser. No. 241,442, filed Nov. 30, 1962. Briey, the core 12includes an aperture 24, a driving leg 27 [and a shunt leg 28. Thecoupling windings 20 and 21 associated with the core 12 are linked in afigure 8 configuration to the ferromagnetic material surrounding theaperture 24. Moreover, since the windings 20 and 21 are shown in FIG. 1as coupled in opposite pol'arities to the core 12, these windings areinductively linked in an opposite relative orientation to the materialon either side of the aperture 24. Finally, the receiving winding 2512is coupled in opposing polarities to the driving and shunt legs 27 and28 whereas the transmitting winding 2612 is linked in a like sense tothese core legs. One terminal of each of the windings 2512 and 2612 isshown grounded in FIG. 2, while the other winding terminals areconnected to the clock sources 73 and 72, which correspond to the @s and@.1 phase symbols, and :also correspond to the receive and transmitnumerals 3 and 2 shown associated therewith in FIG. 1.

The Fore 12 initially resides in a maximum remanent ux condition whichis shown in FIG. 2B. When the winding 2512 is energized during .areceiving cycle (C113), a new ux perturbation is established around theaperture 24 in a clockwise or counter-clockwise direction respectivelyshown in FIGS. 2C and 2D, when a binary l or 0 signal current,respectively, coincidentally ows in the associated incoming winding 20(not shown in FIGS. 2C 'and 2D). When the transmitting winding 2612 islater activated during a transmitting cycle (Q2), a signal is induced inthe intrastage coupling winding 21 in a polarity which depends upon theresidual ux condition around the aperture 24. It is noted that no fluxchange can be elected around the core aperture 24 if neither thereceiving nor transmitting winding 2512 or 2612 is enabled and,therefore, no signals are induced by the core 12 in either of thewindings 20 or 21 coupling the aperture 24 under these conditions.

For purposes of clearly illustrating the instant branching shiftregister, the cores 11 through 18, along with all other ferromagneticcore elements, are represented by standard mirror symbology in FIG. 1.Accordingly, the

clockwise and counter-clockwise ux perturbations around the coreapertures 24 are transformed into up and down tlux states in FIG. 1,while the initial remanent core condition is hereinafter described as aneutral signal ilux state. A detailed description of the mirrorsymbology employed herein is described by M. Karnaugh in the Proceedingsof the I.R.E., May 1955, at page 570. Moreover, since the receiving andtransmitting windings 25 and 26 are not coupled to the signal aperturesincluded in the FIG. 1 cores, these windings are not shown connectedthereto in this illustration.

At this point, a typical sequence of circuit operation characterizingthe shift register stages 10 will be described. More particularly,`assume that the cores 11 through 18 of the specilically illustratedstage 10 included in the register branch 3i) initially reside in theirneutral, initial magnetic condition indicated by the horizontal dashmarks in the upper row in FIG. 3. Further, let the digital terminal 40supply a binary l signal to the stage 10 incoming winding 20 via theremaining branch 30 shifting stages 10, which signal comprises apositive current ilowing in the direction of a vector shown in FIG. 1during clock phase @3, and a negative current ilowing in the directionof a vector 101 during the next following clock phase, viz. @4.

During clock phase @3, the clock source 73 energizes the receivingwindings 2511 and 2512 coupled to the cores 11 and 12. Since the cores11 and 12 are enabled during the I 3 clock interval, the positive binaryl signal current switches these cores to an upward storage state asindicated in the second row in FIG. 3. However, as the cores 13 and 14are not enabled during this time interval, the energized incomingwinding 20 has no effect thereon. In addition, the flux switched in thecores 11 and 12 induces equal and opposite voltage signals in theintra-stage coupling loop 21 responsive to the opposing couplingpolarities with which this winding couples these cores. Hence, thewinding 21 is not energized during the b2 operative cycle.

The @.1 clock voltage signal is next generated and supplied by thesource 74 to the core receiving windings 2513 and 251.1 coincident intime with the negative portion of the incoming binary l signal.Accordingly, the cores 13 and 14 are also set to an upward magneticcondition, as seen in the third row in FIG. 3 associated with the clockinterval 41.1. In correspondence with the circuit operation describedabove for the previous @3 interval, the cores 11 and 12 are unaffectedby the negative incoming signal since the receiving windings 2511 and2512 associated therewith `are not enabled at this time. Further, theflux switched in the cores 13 and 14 induces cancelling signals in theintrastage coupling winding 21.

Responsive to the next clock pulse supplied by the r1 source 71 to thetransmitting windings 2611 and 2613 and to the receiving windings 2515and 2516, the cores 11 and 13 are each driven to their initial, neutralsignal condition. Accordingly, each of these cores induces a current inthe intra-stage coupling loop 21, in the direction of a vector shown inFIG. l, which is operative to set the enabled receiving cores 15 and 16to an upward storage state. It is observed that the incoming andoutgoing stage 16 windings 20 and 22 are not activated during the I 1interval, since the switched cores 11 and 13, and 15 and 16 `arerespectively linked thereto in opposite polarities, and hence induceopposing potentials therein. Thus, during the intra-stage signaltransmission process, the specic shifting stage 10 under considerationis isolated from contiguous stages. The storage states for the cores 11through 18 following the I 1 clock phase are shown in the correspondingrow in FIG. 3.

During the 2 clock interval, a mode of signal propagation parallelingthat described above for I1 obtains, with the cores 12 and 14 beingneutralized and the receiving cores 17 and 18 being set to an upwarddirection by a negative current which llows in the coupling loop 21 in adirection given by a vector 111 shown in FIG. 1. It is noted that thepositive and negative currents owing in the intra-stage winding 21during the @l and @2 clock intervals correspond to the respectiveportions of the original incoming binary 1 signal.

When the clock source 73 supplies the next cyclically recurring 3signal, the cores 15 and 17 are neutralized responsive to the enabledtransmitting windings 2616 and 2617 respectively coupled thereto. Theflux switched in these cores induces additive positive signals in thestage outgoing winding 22 in the direction given by a vector 130, andfurther induces equal and opposite cancelling voltages in theintra-stage winding 21 hence avoiding any backward signal propagation.Similarly, during the next clock phase, viz., @4, cores 16 and 18 areneutralized thereby inducing negative signals in the outgoing winding 22in the direction of a vector 131, while not energizing the intra-stagewinding 21.

Hence, it is seen that the incoming binary l signal received by theshifting stage 10 during the clock periods @3 and @4 is supplied to thenext following shift register stage during the next recurring @3 and 4clock phases. A similar sequence of circuit operations occurs forreceived binary 0 digits, with each of the vertically upward vectorsshown in FIG. 3 being replaced by a downward orientated arrow.

As noted hereinabove, the branch point register stage 55 is employed toselectively control the infomation flow among the shifting branches 30through 33. The stage 55 includes an incoming winding 50, an intra-stagecoupling winding 51, and a iirst set of cores 61 through 64 whichfunction in a manner identical to the corresponding elements included inthe shifting stages 10, viz., the windings 20 and 21 and the cores 11through 14. More specilically, a binary digit is inserted into the cores61 through 64 by an activated incoming winding 50 during clock phases @3and 14, and a like digital signal is induced in the intra-stage winding51 during the succeeding @l and 2 clock phases.

In generalized terms, the intra-stage coupling winding 51 is furtherinductively linked to a second set of 2n cores (65 through 68 in FIG.1), wherein ZH-l shifting branches (three in FIG. 1) converge on Ithebranching stage 55. A plurality of 211-1 mutually orthogonal windings,including the intra-stage winding 51, are selectively coupled to the21l1 cores, with each of these windings being associated with adifferent register branch. The windings are orthogonal in the sense thatreceiving and transmitting clock energizations supplied to any half(2n-1) of the 2n cores will induce a net signal in only a selected oneof the 211-1 windings, and induce cancelling signals in the remainder ofsuch windings. A procedure for dening the polarity in which the 211-1orthogonal windings are linked to the 2n cores is given hereinafter.

With regard to the arrangement shown in FIG. l, the stage 55 second coreset includes 211:4 01:2) cores 65 through 68, corresponding to the2n-1=3 shift register branches 30 through 32. Coupled to the cores 65through 68 are 21k-1:3 mutually orthogonal windings including theintra-stage loop 51 associated with the register branch 30, and twooutgoing windings 52 and 53 respectively connected to the shiftingbranches 31 and 32.

The clock distribution circuit 70 is employed to selectively connect thetransmitting windings 26 coupled to the cores 65 through 68 to the :P3and @4 clock sources 73 and 74 in a manner determined by the desiredsignal propagation path. For purposes of concreteness, assume thatinformation is to be transmited from the digital terminal 40 to theterminal 42. Accordingly, the core transmitting windings 2666 and 2668,and the windings 2666 and 2667 are respectively connected by thedistribution circuit 70 to the clock sources 73 and 74, as indicated bythe transmit-to-winding 53 (Tr-53) numerals 3, 4, 4 and 3 shown in FIG.l. It is noted that the clock distribution circuit 70 may comprise anymatrix switching array, including either mechanical or electroniccrosspoint connectors, to selectively join the clock sources 73 and 74with the core transmitting windings 2666 through 2653.

Assume now that the digital terminal 40 in conjunction with the shiftingbranch 30 supplies a binary l signal, comprising sequential positive andnegative portions coincident in time with the I 3 and @4 clock phases,to the branching point stage 55. During the @3 and r4 clockenergizations supplied by the sources 73 and 74, the cores 61 and 62 andthen 63 and 64 are set to an upward magnetic state by a mode of circuitfunctioning described in detail hereinabove with respect to the stage 10cores 11 through 14.

When the clock source 71 next supplies a clock signal to the core 61 and63 transmitting windings 2661 and 2663, a positive signal current isinduced in the intra-stage winding 51 in a direction given by a vector140 shown in FIG. l. Since the receiving windings 2566 and 2566 areenergized during this clock interval, the cores 65 and 66 are switchedby the energized winding 51 from their initial, neutral signal stateshown in the upper row in FIG. 4 to an upward storage direction, asindicated in the second 61) row in FIG. 4. However, as the stage 55outgoing windings 52 and 53 are coupled in opposing polarities to thecores 65 and 66, the above-noted iiux changes transpiring therein induceequal and opposite cancelling signals in these windings, Hence, no netsignal is detected by either of the shift register branches 31 or 32 atthis time. Similarly, during the next occurring @2 clock phase, thecores 67 and 68 are set upward by a negative current, in the directionof a vector 141, which iiows in the intrastage link 51 during thisinterval. Moreover, no net signals are induced in either of the outgoingwindings 52 and 53 by the ux changes effected in the cores 67 and 68.

Responsive to the @3 clock voltage pulse supplied by the source 73 tothe transmitting windings 2666 and 2666 via the clock distributioncircuit 70, the cores 65 and 68 are driven to their neutral signalcondition, as indicated in the fourth row of FIG. 4 associated with the#b3 clock phase. Since the outgoing winding 53 is coupled in a likepolarity to the cores 65 and 68, these cores are operative to induce anet positive signal therein in the direction given by a vector 150.Accordingly, this positive current is supplied by the enabled outgoingwinding 53 to the shifting branch 32. However, as the enabled cores 65and 68 are coupled in an opposite polarity to each of the windings 51and 52, no net energization is induced therein and, therefore, nosignals are directed at this time towards either of the shiftingbranches 30 or 31. Similarly, during the da, clock interval, the cores66 and 67 are driven to a neutral signal condition thereby inducing anegative current, in the direction of a vector 151 shown in FIG. 1, inthe outgoing stage 55 winding 53. Moreover, since the windings 51 and 52are each coupled in opposite polarities to the cores 66 and 67, thesewindings are not activated at this time.

Hence, the branch point register stage 55 has been shown by the above toaccept a binary digit supplied thereto by the register branch 30 duringthe r3 and @4 clock intervals, and to supply a like digit to theshifting branch 32 via the outgoing winding 53 included therein duringthe next following @a and @4 periods. In a similar manner, when thetransmitting windings 2666 through 2666 are respectively connected tothe clock sources 73 and 74 in accordance with the transmit-to-winding52 (Tr-52) numerals "3, 4, 3, and 4 shown in FIG. 1, the informationsupplied by the branch 30 is supplied by the stage 55 to the shiftingbranch 31 after a cyclic delay of four clock phases. The storage stateswhich obtain in the transmit-to-branch 31 mode of operation are depictedin the two bottom rows in FIG. 4.

It is noted at this point, that the FIG. 1 shift register arrangementmay advantageously be operated to propagate information in aright-to-left direction, in place of the left-to-right translation pathconsidered above, by simply constraining the sources 71 through 74 tosupply the clock phase energizations in the reverse order, viz., @4through @1. The details of such a mode of operation follow from acircuit analysis identically paralleling that given above forleft-to-right signal translation.

It remains now to describe a procedure for determining the polarity withwhich each of the generalized plurality of 2D-1 mutually orthogonalcoupling windings are linked to the 2l1 second set of cores included ina branching register stage 55. The following describes a recursivemethod for eecting this polarity determination, wherein binary n1 and 0character respectively represent the two alternative senses in which awinding may be coupled to a magnetic core element.

PROCEDURE Begin with the n=1 case, where there is only one winding ofinterest, viz., 10, which is coupled to the rst of 21:2 cores in the lsense, and coupled to the other core in a O polarity. Construct thewinding set for n=2 as follows:

(1) Write the set for n=1 followed by the set for n=1. We then have1010.

(2) Below the results of step l write the set for n=1 followed by theset for n=1 complemented. We then have: 1010, 1001.

(3) Following the product of step 2, add a set consisting of first halfls and second half s. We then have: 1010, 1001, 1100.

Each of the above-listed three digital words denes one winding for 11:2.With reference to the branching register stage 55 shown in FIG. l, thethree rows respectively correspond to the mutually orthogonal windings52, 53, and 51.

(4) Repeat for all larger n by employing the previous set in each case.

For example, for n=3,

Step 1:

Step 2:

Step 3:

with these seven digital words deiining the pattern in which the 23-1=7windings link the 23:8 cores.

summarizing, an illustrative shift register made in accordance with theprinciples of the present invention employs a plurality ofmultiapertured cores to bilaterally propagate digtial informationthrough selected register branches. The arrangement includes a pluralityof balanced magnetic core stages, with a digital bit translating throughan associated shifting stage responsive to four impressed clock phasesignals.

A linked set of 2n cores is included in the shifting stage associatedwith each register .branching point to selectively Y route informationamong a total of 2n-1 incoming and outgoing branches via 2-1 mutuallyorthogonal coupling windings. The particular information propagatingpath is dependent upon the specific manner in which the clock signalsare supplied to the cores.

It is to be understood that the above-described arrangements are onlyillustrative of the application of the principles of the presentinvention. Numerous other arrangements may be devised by those skilledin the art without departing from the spirit and scope of thisinvention. For example, the clock sources 71 through 74 mayadvantageously comprise current, and not voltage supplying embodiments.In such an organization, all receiving and transmitting windings 25 and26 associated with a like clock source would be serially interconnected,and further connected to that source.

What is claimed is:

1. In combination, 2n square loop magnetic storage elements, where n isany positive integer greater than 1, 2-1 signal windings coupled in amutually magnetically orthogonal relationship to said elements, andiirst clock means for sequentially switching a rst selected set of Znnlof said elements and then switching the remaining 211-1 of saidelements.

2. A combination as in claim 1 further comprising second clock means forsequentially switching a second set of 2-1 of said elements and thenswitching the remaining Zur-1 of said cores.

3. A combination as in claim 2 further comprising 2-1 digitalinformation translating channels each connected to a different one ofsaid mutually orthogonal signal windings.

4. A combination as in claim 3 wherein said first and second clock meanscomprise a plurality of clock sources for sequentially supplying cyclicclock pulses, and a clock distribution circuit connected to said clocksources.

5. A combination as in claim 4 wherein each of said informationtranslating channels comprises a plurality of cascaded shift registerstages.

6. A combination as in claim 5 wherein each of said shift registerstages comprises a rst set of four elements and a second set of fourelements, an intra-stage coupling winding linked to each elementincluded in said first and said second four element sets, an incomingwinding coupled to each element included in said iirst four element set,and an outgoing winding coupled to each element included in said secondfour element set, said incoming and outgoing windings being respectivelycoupled to the four element set associated therewith in an orthogonalrelationship with said intra-stage coupling winding.

7. A combination as in claim 6 further comprising a plurality of digitalterminals each connected to a diterent one of said informationtranslating channels.

8. A combination as in claim 1 wherein said 211-1 orthogonal windingsare coupled to said 2n elements in accordance with a binary matrix [Bn]where [Bn-1] [Bn-1] [Bnl= [Bn-1] [B-1] [1. ..1][0...0]

wherein [Bn 1]=[10] for n=2, and wherein [Bn 1] comprises [Bn 1] withall the binary digits complemented.

9. In combination,

a plurality of square loop magnetic cores,

a plurality of signal windings coupled in a mutually magneticallyorthogonal relationship to said cores, and

first clock means coupled to said cores for sequentially switching aiirst set of said cores and then switching the remainder of said cores.

10. A combination as in claim 9 further comprising second clock meanscoupled to said cores for sequentially switching a second set of saidcores, and then switching the remainder of said cores.

11. A combination as in claim 10 further comprising a plurality ofdigital information translating channels each connected to a diterentone of said mutually orthogonal signal windings.

12. A combination as in claim 11 wherein said first and second clockmeans comprise a plurality of clock sources for sequentially supplyingcyclic clock pulses, and a clock distribution circuit connected to saidclock sources.

13. A combination as in claim 12 wherein each of said informationtranslating channels comprises a plurality of cascaded shift registerstages.

14. A combination as in claim 13 wherein each of said shift registerstages comprises a first set of four cores and a second set of fourcores, an intra-stage coupling winding linked to each core included insaid first and second core sets, an incoming winding coupled to eachcore included in said rst set of four cores, and an outgoing windingcoupled to each core included in said second set Of four cores, saidincoming and outgoing windings being respectively coupled to the fourcore set associated therewith in an orthogonal relationship with saidintra-stage coupling winding.

15. A combination as in claim 14 further comprising a plurality ofdigital terminals each connected to a different one of said informationtranslating channels.

16. A combination as in claim 9 wherein said signal windings are coupledto said cores in accordance with a binary matrix [BHL Where [Bn-xl[Bn-4] [Buti: [Bn-'1] [B-1] [1...1] [O...0]

wherein [Bn 1]=[l0] for n=2, and wherein [Bn 1] comprises [Bn 1] witheach of the elements therein reversed to their alternate binarycharacter.

17. A combination as in claim 16 further comprising digital terminalmeans connected to each of said orthogonal windings.

18. In combination, a plurality of information channels, an informationshifting stage connected to each of said channels, said shifting stageIcomprising a plurality of balanced magnetic multiapertured cores and aplurality ofmagnetically mutually orthogonal windings selectivelycoupled thereto and respectively connected to said information channels.

-19. In combination, a plurality of balanced magnetic cores, Windingmeans coupled to each of said cores to enable ferromagnetic switchingtherein, a plurality of magnetically mutually orthogonal windingscoupled to said cores, first clock means connected to said winding meansfor selectively enabling a first set of said cores, and second clockmeans connected to said winding means Y for enabling the remainder ofsaid cores.

References Cited UNITED STATES PATENTS '3,004,246 10/ 1961 Harper340-174 STANLEY M. URYNOWICZ, JR., Primary Examiner

